The present invention relates to a data acquisition method and circuit, and, more particularly, to a protocol controller for IEEE 1394, suitable for a data processor which conforms to IEEE 1394 standards or serial interface standards.
Recently, due to the progress in multimedia systemization, various kinds of peripheral devices have been connected to a personal computer. Such peripheral devices include a digital camera, a digital VCR and a color printer. Such peripheral devices handle vast amounts of audio and video data and demand fast data transfer between a computer and its peripheral devices. Attention has been paid to IEEE 1394, which defines serial interface standards, as an interface suitable for such fast data transfer.
Data transfers which conform to IEEE 1394 use a data line and a strobe line. A data strobe (DS) link system is preferably employed to acquire data which is output from the data line. The data acquisition according to the DS link system also demands fast data transfer and increased amount of data to be transferred.
The DS link system has a data line and a strobe line provided in a bus between a computer, such as a personal computers, and peripheral devices and also in a bus between the peripheral devices. Transfer data is output onto the data line, while a strobe signal is sent to the strobe line. When identical transfer data bit D1 is transferred serially from the data line (when the transfer data bit D1 is not inverted), as shown in FIG. 1, a strobe signal SB is inverted in accordance with the transfer of the transfer data bit D1. When different transfer data bits D1 are transferred (when the transfer data bit D1 is inverted), the strobe signal SB is not inverted.
More specifically, suppose that the same transfer data bit D1, "1", is transferred twice, consecutively. In this case, when the strobe signal SB corresponding to the first transfer data bit D1 is "1", the next strobe signal SB is inverted to "0". When the first strobe signal SB is "0", on the other hand, the next strobe signal SB is inverted to "1". When the same transfer data bit D1 of "0" is transferred twice consecutively, the strobe signal SB is also inverted as mentioned above.
A description will now be given of the case where the transfer data bit D1 of "1" and transfer data bit D1 of "0" are transferred successively. When the strobe signal SB corresponding to the first transfer data bit D1 of "1" is "1", the next strobe signal SB stays "1". When the first strobe signal SB is "0", the next strobe signal SB likewise remains "0". When the transfer data bit D1 of "0" and transfer data bit D1 of "1" are transferred successively, the output of the same strobe signal SB of "1" or "0" is maintained as described above coincidence and uncoincidence of the transfer data bit D1 and the strobe signal SB. In this manner, every time one transfer data bit D1 is transferred, coincidence and uncoincidence of the transfer data bit D1 and the strobe signal SB are alternately repeated. In the DS link system, a clock signal for acquiring data is generated by performing an exclusive OR of the transfer data bit D1 and the strobe signal SB which alternately repeat such coincidence and uncoincidence.
FIG. 2 is a block diagram of a conventional data acquisition circuit which generates a clock signal to acquire data. The data acquisition circuit includes first and second D flip-flops 51 and 52, an exclusive OR gate 53 and an inverter 54. The exclusive OR gate 53 receives a transfer data bit D1 and a strobe signal SB, and outputs a clock CLK. The clock signal is low or "0" when D1 and SB match or coincide with each other and high or "1" when D1 and SB do not match with each other. A delay circuit 55 serves to delay the clock CLK from the exclusive OR gate 53.
The first flip-flop 51 receives the inverted clock CLK via the inverter 54, latches the current transfer data bit D1 in response to the falling of the clock CLK, and then outputs data D1even. This data D1even represents the transfer data bit D1 when the transfer data bit D1 coincides with the strobe signal SB.
The second flip-flop 52 latches the current transfer data bit D1 in response to the rising of the clock CLK, and then outputs data D1odd. This data D1odd represents the transfer data bit D1 when the transfer data bit D1 and the strobe signal SB do not coincide with each other. In this way, the transfer data bit D1 which is transferred from the data line is output from the first and second flip-flops 51 and 52 alternately in accordance with the clock CLK.
As shown in FIG. 3, the inversion timing of the clock CLK is delayed by time td from the inversion timing of the transfer data bit D1 or the strobe signal SB. The delay time td is produced by the delay circuit 55. This delay time td provides a setup time for the first and second flip-flops 51 and 52 to securely latch the transfer data bit D1.
The period of the clock CLK tends to become shorter as data transfer becomes faster. The shortened clock period makes it difficult to secure the sufficient hold time for the first and second flip-flops 51 and 52 to hold the transfer data bit. To provide a sufficient hold time, the setup time is set as short as possible. It is however very difficult to design the delay circuit 55 to make the setup time as short as possible. Further, the manufacture of such delay circuits requires very precise technology and often has in a poor yield for the circuits.
Accordingly, it is an objective of the present invention to provide a data acquisition method and circuit which does not need an adjustment of the setup time or hold time for data transfer.